 SU.HARDW.PC.CPU (2:5020/299)  SU.HARDW.PC.CPU 
 From : Lesha Bogdanow                      2:5095/9        Wed 13 Mar 96 07:08 
 Subj : Cyrix 5x86 (M1SC)                                                       


    ⮡   p - ,    Cyrix' (p M1 :( ):

=== Cut ===
 The configuration registers on Cyrix processors
 ===============================================

 Most Cyrix processors contain special registers, which can be accessed via I/O
 operations on port 22h (command port) and 23h (data port). The following short
 sequences should be used to read or write such a register:

   READ:  OUT  22h,reg#                WRITE:  OUT  22h,reg#
          IN   23h,value                       OUT  23h,value

 Remember, that some short delays should be included between two port accesses!

 The Cyrix Cx486SLC/DLC and TI486 processors contain the following registers:

 ------------------------------------------------------------------------------
 name  reg# description
 ------------------------------------------------------------------------------
 CCR0  C0h  configuration control register #0 (=0h after reset)
            bit7     SUSP - enable SUSPI# input pin and SUSPA# output pin
                       1=enabled, 0=disabled (=pins float)
            bit6     CO - cache organisation
                       1=direct mapped, 0=2-way set assiociative
            bit5     BARB - enable L1 cache flush when beginning HOLD state
                       1=enabled, 0=disabled
            bit4     FLUSH - enable FLUSH# input pin
                       1=enabled, 0=disabled
            bit3     KEN - enable KEN# input pin
                       1=enabled, 0=disabled
            bit2     A20M - enable A20M# input pin
                       1=enabled, 0=disabled
            bit1     NC1 - caching for 640K..1M area (bug in A4/A5-step?)
                       1=disabled (=never), 0=enabled (but see NCRx!)
            bit0     NC0 - caching for 1M..1M+64K area (real and V86 mode)
                       1=disabled, 0=enabled
 ------------------------------------------------------------------------------
 CCR1  C1h  configuration control register #1 (=xxxxxxx0b after reset)
            bit7..1  reserved
            bit0     RPL - enable RPLSET# and RPLVAL# pins
                       1=enabled, 0=disabled (=pins float)
 ------------------------------------------------------------------------------
 NCR1  C4..C6h  non-cacheable region #1 (=0h,0h,0Fh after reset (on SLC))
 NCR2  C7..C9h  non-cacheable region #2 (=0h,0h,0h after reset)
 NCR3  CA..CCh  non-cacheable region #3 (=0h,0h,0h after reset)
 NCR4  CD..CFh  non-cacheable region #4 (=0h,0h,0h after reset)
       +0h  bit7..0  address bits A31..A24 of non-cacheable region start
                       (reserved on SLC, see value after reset)
       +1h  bit7..0  address bits A23..A16 of non-cacheable region start
       +2h  bit7..4  address bits A15..A12 of non-cacheable region start
            bit3..0  size of non-cacheble block
                       0000=dis.    0100=32K     1000=512K    1100=8M
                       0001=4K      0101=64K     1001=1M      1101=16M
                       0010=8K      0110=128K    1010=2M      1110=32M
                       0011=16K     0111=256K    1011=4M      1111=4G
 ------------------------------------------------------------------------------

 The Cyrix Cx486S/S2/D/D2/DX/DX2 processors contain the following registers:

 ------------------------------------------------------------------------------
 name  reg# description
 ------------------------------------------------------------------------------
 CCR1  C1h  configuration control register #1 (=0h after reset)
            bit7..5  reserved
            bit4     N_LOCK - negate LOCK#
                       1=enabled, 0=disabled
            bit3     MMAC - enable main memory accesses when CCR1.SMAC=1
                       1=enabled, 0=disabled
            bit2     SMAC - enable SMM memory accesses with SMAADS# active
                       1=enabled (SMI# ignored), 0=disabled
            bit1     SMI - enable SMM pins (SMI# I/O pin and SMADS# output pin)
                       1=enabled, 0=disabled (=pins float)
            bit0     RPL - enable RPLSET# and RPLVAL# pins
                       1=enabled, 0=disabled (=pins float)
 ------------------------------------------------------------------------------
 CCR2  C2h  configuration control register #2 (=0h after reset)
            bit7     SUSP - enable SUSP# input pin and SUSPA# ouput pin
                       1=enabled, 0=disabled (=pins float)
            bit6     BWRT - enable (16byte WB) burst write cycle
                       1=enabled, 0=disabled
            bit5     BARB - enable cache coherency on bus arbitration
                       1=enable write back of all dirty cache data when HOLD is
                         requered and prior to asserting HLDA
                       0=disabled
            bit4     WT1 - caching for 640K..1M area
                       1=force all writes to 640K..1M area that hit in cache
                         issued on the external bus
                       0=disabled
            bit3     HALT - enable entering suspend mode on HLT inctructions
                       1=enabled, 0=disabled
            bit2     LockNW - prohibits changing the state of the CR0.NW bit
                       1=enabled (=prohibited), 0=disabled (=allowed)
            bit1     WBAK - enable WB cache pins (INVAL, WM_RST, HITM#)
                       1=enabled, 0=disabled (=pins float)
            bit0     reserved
 ------------------------------------------------------------------------------
 CCR3  C3h  configuration control register #3 (=0h after reset)
              (not on Cyrix Cx486S A-step processors but on newer Cx486SLC/DLC)
            bit7..2  reserved
            bit1     NMIEN - enable NMI during SMM
                       1=enabled, 0=disabled
            bit0     SMI_LOCK - SMM register lock
                       1=CCR1.bit3..1 and CCR3.bit1 can't be changed in SMM;
                         CCR3.bit0 can be changed in SMM; only RESET clears it!
                       0=disabled
 ------------------------------------------------------------------------------
 SMAR  CD..CFh  SMM address region (=0h,0h,0h after reset)
       CDh  bit7..0  address bits A32..A24 of SMM region start
       CEh  bit7..0  address bits A23..A16 of SMM region start
       CFh  bit7..4  address bits A15..A12 of SMM region start
            bit3..0  size of SMM region
                       0000=dis.    0100=32K     1000=512K    1100=8M
                       0001=4K      0101=64K     1001=1M      1101=16M
                       0010=8K      0110=128K    1010=2M      1110=32M
                       0011=16K     0111=256K    1011=4M      1111=4G
 ------------------------------------------------------------------------------
 DIR0  FEh  device identification register #0
              (not on Cyrix Cx486S A-step processors but on newer Cx486SLC/DLC)
            bit7..0  processor model
              00h - Cx486SLC        08h - Cx486SRu        1Ah - Cx486DX
              01h - Cx486DLC        09h - Cx486DRu        1Bh - Cx486DX2
              02h - Cx486SLC2       0Ah - Cx486SRu2       2xh - Cyrix 5x86
              03h - Cx486DLC2       0Bh - Cx486DRu2       3xh - Cyrix 6x86 (?)
              04h - Cx486SRx        10h - Cx486S
              05h - Cx486DRx        11h - Cx486S2
              06h - Cx486SRx2       12h - Cx486Se         FFh - probably not a
              07h - Cx486DRx2       13h - Cx486S2e              Cyrix processor
 ------------------------------------------------------------------------------
 DIR1  FFh  device identification register #1
              (not on Cyrix Cx486S A-step processors but on newer Cx486SLC/DLC)
            bit7..4  processor revision (0..Fh)
            bit3..0  processor stepping (0..Fh)
 ------------------------------------------------------------------------------

 The Cyrix 5x86 processor contains the following registers:

 ------------------------------------------------------------------------------
 name  reg# description
 ------------------------------------------------------------------------------
 CCR1  C1h  configuration control register #1 (=0h after reset)
            bit7..4  reserved
            bit3     MMAC - enable main memory accesses when CCR1.SMAC=1
                       1=enabled, 0=disabled
            bit2     SMAC - enable SMM memory accesses with SMAADS# active
                       1=enabled (SMI# ignored), 0=disabled
            bit1     SMI - enable SMM pins (SMI# I/O pin and SMADS# output pin)
                       1=enabled, 0=disabled (=pins float)
            bit0     reserved
 ------------------------------------------------------------------------------
 CCR2  C2h  configuration control register #2 (=0h after reset)
            bit7     SUSP - enable SUSP# input pin and SUSPA# ouput pin
                       1=enabled, 0=disabled (=pins float)
            bit6     BWRT - enable (16byte WB) burst write cycle
                       1=enabled, 0=disabled
            bit5     reserved
            bit4     WT1 - caching for 640K..1M area
                       1=force all writes to 640K..1M area that hit in cache
                         issued on the external bus
                       0=disabled
            bit3     HALT - enable entering suspend mode on HLT inctructions
                       1=enabled, 0=disabled
            bit2     LockNW - prohibits changing the state of the CR0.NW bit
                       1=enabled (=prohibited), 0=disabled (=allowed)
            bit1     WBAK - enable WB cache pins (INVAL, WM_RST, HITM#)
                       1=enabled, 0=disabled (=pins float)
            bit0     reserved
 ------------------------------------------------------------------------------
 CCR3  C3h  configuration control register #3 (=?0h after reset)
            bit7..4  MAPEN - select active control register set for D0h..FDh
                       0001=default (others are not valid at the moment)
            bit3     SMIACT - enable Intel compatible SMM (i486SL?)
                       1=enabled, 0=disabled
            bit2     LINBRST - enable linear address sequence for burst cycles
                       1=enabled, 0=disabled
            bit1     NMIEN - enable NMI during SMM
                       1=enabled, 0=disabled
            bit0     SMI_LOCK - SMM register lock
                       1=CCR1.bit3..1 and CCR3.bit1 can't be changed in SMM;
                         CCR3.bit0 can be changed in SMM; only RESET clears it!
                       0=disabled
 ------------------------------------------------------------------------------
 CCR4  E8h  configuration control register #4
            bit7..6  reserved
            bit5     FP_FAST - enable fast FPU exception reporting
                       1=enabled, 0=disabled
            bit4     DTE_EN - enable directory table entry cache
                       1=enabled, 0=disabled
            bit3     MEM_BYP - enable memory bypassing
                       1=enabled, 0=disabled
            bit2..0  IORT - I/O recovery time
                       xxx=2^0..7 bus clock cycles
 ------------------------------------------------------------------------------
 CR    F0h  configuration register
            bit7     SMCC - self modifying code checking
                       1=disabled, 0=enabled
            bit6..3  reserved
            bit2     CCLK - core clock
                       1=1/2external bus clock, if bus is idle, 0=normal
            bit1..0  clock mode core/bus
                       11=3:1?, 10=2:1?
 ------------------------------------------------------------------------------
 CDR   20h  chip debug register
            bit7     LSO - load/store ordering
                       1=strong, 0=weak
            bit6     BTBTR - enable BTB test register
                       1=enabled, 0=disabled
            bit5     reserved
            bit4     MLR - enable reordering of misaligned loads
                       1=enabled, 0=disabled
            bit3     AIS - enable all instructions stalled to serialize pipe
                       1=enabled, 0=disabled
            bit2     LOOP - enable loopmode
                       1=enabled, 0=disabled
            bit1     BTB - enable BTB
                       1=enabled, 0=disabled
            bit0     RS - enable return stack
                       1=enabled, 0=disabled
 ------------------------------------------------------------------------------
 ???   60h  unknown register
 ???   61h  unknwon register
 ------------------------------------------------------------------------------
 SMAR  CD..CFh  SMM address region (see description above!)
 ------------------------------------------------------------------------------
 DIR0  FEh  device identification register #0 (see description above!)
 DIR1  FFh  device identification register #1 (see description above!)
            A DIR1 value of 13h indicates the revision 1.30, as 15h indicates a
            revision 1.50 processor. I don't know how the sub-stepping (so i.e.
            1.41 or 1.42) can be differed. Do you?
 ------------------------------------------------------------------------------

=== Cut ===


          訬 ﬨ,
                        
--- p /2 2.50.A0715+
 * Origin: Boggy Place. Troitsk. (2:5095/9)


