 SU.HARDW.PC.MOTHERBOARD (2:5020/299)  SU.HARDW.PC.MOTHERBOARD 
 From : Alex Iliynsky                       2:5020/23.559   Tue 24 May 94 00:20 
 Subj : Pentium & Optimization                                                  

Hi All!

   襫  ᥡ ᮪  p  DDJ,
  p묨 묨  P5,  p樯 ⨬樨.
  ᮪ 㦥   ru.hacker     ru.hacker.uue.
  ⥬   -  让.


  p襫 p DDJ  쥩 p ⨬  Pentium -
    p  ,  , p, p  
 p묨 - ... :)

 H p樨:

 CMPXCHG8B - compare and exchange 8 bytes

 CPUID       CPU identification (EAX is input)
             for EAX = 0; returns vendor string in EBX,EDX,ECX -
                    ᫨  訡 GenueIntel :)
             for EAX = 1; returns EAX[0:3]      stepping number
                                  EAX[4:7]      model number
                                  EAX[8:11]     family number
                                  EAX[12:31]    reserved
                                  EBX,ECX       reserved (0)
                                  EDX - feature flag -
                     - p 稥 p  -
                    ⨯ ᮯp  pp , 筮  ,   
ᠭ.

  RDMSR      Read from Model Specific Register (ECX is register number)
  WRMSR      Write to Model Specific Register (ECX is register number)
  RSM        Resume from System Managment Mode
  RDTSC      Read Time Stamp Counter ***
  MOV        Move to/from Control registers (new registers)


  ᥬ ⮬ 祣  ᪠ p RDTSC - p᭠ p -
 p頥 ⥪饥 祭 p 稪, p pp
  cycle  EDX:EAX - p 66Mhz ⮣ 稪 墠⠥  8800 ...

 Opcode 0FH 31H

  ᥬ ⠫묨  p頩 - Intel Pentium Processor
 User's Manual, Volume 3: Architecture and Programming Manual
 (Intel #2411430-001) Appendix A (page A-7) -  opcode map.

 H p ⨬ -

 U pipe p뢠  楫᫥  -  ᫥
  p pairing. V pipe 믮 ⮫쪮 "p" p樨,
   p p樨  ᫥騬  p,
  ᫮ ᯠp ᮡ, CPU "ᯠp" p樨 
 稭  믮 p.

 p p樨:

 mov reg,reg        mov reg,mem         mov reg,imm
 mov mem,reg        mov mem,imm         ALU reg,reg
 ALU reg,mem        ALU reg,imm         ALU mem,reg
 ALU mem,imm        INC reg             INC mem
 DEC reg            DEC mem             Push reg
 pop reg            LEA reg,mem         jmp near
 call near          Jcc * near          NOP !!!! :)
 shift reg,1        shift mem,1         shift reg,imm
 shift mem,imm

 : ALU - add,adc,and,or,xor,sub,sbb,cmp,test
      SHIFT - sal,sar,shl,shr,rcl,rcr,rol,rlr (rcl and rcr not pairable with
               immediate)

 p ᯠp:  p

 1. Both instructions must be simple - ᬮp p
 2. Shift/rotate can only be in U pipe.
 3. ADC and SBB can only be in V pipe
 4. JMP/Jcc/CALL can only be in V pipe (Jcc - conditional jump)
 5. Neither instructions can contain both a displasment AND an
    immediate operand.
 6. Prefixed instructions can only be in U pipe (except for 0F for Jcc)
 7. The U pipe instruction must be only one byte in length or it will not pair
    until the second time it executes from the cache.
 8. There can be no read-after-write or write-after-read register
    depedencies between th instructions except for special cases for the
    flag register and the stack pointer (Rules #9 and #10).
 9. The flag register exception allows a CMP or TEST instructions to be
    paired with a Jcc even through CMP/TEST writes the flag and Jcc reads the
    flag.


