 SU.HARDW.OTHER (2:5020/299)  SU.HARDW.OTHER 
 From : Alexej Vladimirov                   2:5100/22.1     Sat 06 May 95 10:51 
 Subj : 24c01a                                                                  


____________________________________________________________________________
  "Serial EEPROM Handbook", 1994. P. 2-3...2-12

24C01A/02A/04A - 1K/2K/4K CMOS Serial Electrically Erasable PROM.
Pin configuration:
                            ======
                       NC -|1 U 14|- NC
                       A0 -|2   13|- Vcc
      =====            A1 -|3   12|- WP
 A0 -|1 U 8|- Vcc      NC -|4   11|- NC
 A1 -|2   7|- WP       A2 -|5   10|- SCL
 A2 -|3   6|- SCL     Vss -|6    9|- SDA
Vss -|4   5|- SDA      NC -|7    8|- NC
      =====                 ======
    DIP, SOIC 24C01A/02A   SOIC 24C04A

DC Characteristics:
                                 min     max             conditions
Vcc detector treshold            2.8     4.5
SCL and SDA pins:
High level input voltage, V    Vcc*0.7  Vcc+1
Low level input voltage, V      -0.3     0.5
Low level output voltage, V              0.4           Iol= 3.2 mA (SDA only)
A1 and A2 pins:
High level input voltage, V    Vcc-0.5 Vcc+0.5
Low level input voltage, V      -0.3     0.5
Input leakage current, uA                10             Vin= 0V to Vcc
Output leakage current, uA               10             Vout= 0V to Vcc
Internal capacitanse, pF                 7.0            Vin/Vout= 0V, f= 1MHz
Operating current, (write), mA           3.5            Fclk= 1MHz, cycle= 1ms
                   (read), mA            0.75
Standby current, uA                      100            SDA=SCL=Vcc= 5V

AC Characteristics:
                                                         min   max   conditions
Clock frequency, kHz                           Fclk            100
Clock high time, us                            Thigh     4.0
Clock low time, us                             Tlow      4.7
SDA and SCL rise time, us                      Tr              1.0
SDA and SCL fail time, us                      Tf              0.3
Start condition hold time, us                  Thdsta    4.0
Start condition setup time, us                 Tsusta    4.7
Data input hold time, ns                       Thddat      0
Data input setup time, ns                      Tsudat    250
Data output delay time, us                     Tpd       0.3   3.5
Stop condition setup time, us                  Tsusto    4.7
Bus free time, us                              Tbuf      4.7
Input filter time constant, ns                 Tl              100  SDA and SCL
Program cycle time, ms                         Twc       0.4    1   byte mode
                                                       0.4*N    N   page mode
Endurance, E/W cycles                                 100000

Bus timing:

              | Tf|       | Thigh  |     Tlow    |            | Tr|
        ______|   |       | ______ |             | _____      |   |___________
      |/       \| |       |/      \|             |/     .     | |/
SCL__/|         |\|______/|        |\___________/|       .....|/|
      |  |      |                  |             |              |
Tsusta|<>|Thdsta|                  |Thddat|Tsudat|        Tsusto|<>| Tbuf  |
________ |      |       ___________|_____ | ___________......      | _____ |
        \|      |      /           |     \|/                       |/     \|
SDA IN   |\_____|____/_____________|_____/|\___________........___/|       |\_
                |                  |
                | Tpd |            |Tpd|
_____________________ | ______________ | _____________________________________
\ /\ /\ /\ /\ /\ /\ /\|/              \|/
SDA OUT_\/_\/_\/_\/_\/|\______________/|\_____________________________________


Current address Read (SDA line):

 S                                     S
 T         A A A     D D D D D D D D   T
 A 1 0 1 0 2 1 0 1 0 7 6 5 4 3 2 1 0 1 O
 R                 A                   P
 T                 C
                   K

Random Read (SDA line):

 S                                     S                                     S
 T         A A A     W W W W W W W W   T         A A A     D D D D D D D D   T
 A 1 0 1 0 2 1 0 0 0 7 6 5 4 3 2 1 0 0 A 1 0 1 0 2 1 0 1 0 7 6 5 4 3 2 1 0 0 O
 R                 A                 A R                 A                   P
 T                 C                 C T                 C
                   K                 K                   K



Byte Write (SDA line):

 S                                                       S
 T         A A A     W W W W W W W W   D D D D D D D D   T
 A 1 0 1 0 2 1 0 0 0 7 6 5 4 3 2 1 0 0 7 6 5 4 3 2 1 0 0 O
 R                 A                 A                 A P
 T                 C                 C                 C
                   K                 K                 K


A0, A1, A2 - device address. Up to 8 24C01A/02A or up to 4 24C04A can be
connected to the bus. A0 has no function on 24C04, but must be tied to Vss or
Vdd.

W0...W7 - word address

D0...D7 - data

pin WP protects upper half of the memory on 24C02A and 24C04A, if it is
connected to Vcc. The device will accept slave and word addresses but if the
memory accessed is write protected by the WP pin, the 24C02A/04A will not
generate an acknowledge after the first byte of data has been received, and thus
the program cycle will not be started when the STOP condition is asserted.
It has no effect on 24C01A.

Page - maximum number of bytes that can be programmed on a single write cycle.
The 24C04A page is 8 bytes long, the 24C01A/02A page is 2 bytes long.

___________________________________________________________________________

--- GoldED/386 2.50.B0822+
 * Origin: * AV_Point - Riga, Latvia * (2:5100/22.1)

