 SU.HARDW (2:4790/10.6)  SU.HARDW 
 From : Alexej Vladimirov           2:4790/10.6             20 May 93  14:30:12
 Subj : 93C46 -   ???


GZ>         奬,   , ᯮ ᥩ 稯,
GZ> 砥  93C46,  뢠 Serial NVRAM. H   ᪠
GZ> ᥧ騩 All,    ᠭ ᥣ ।???

  "Microchip data book", 1992. P. 1-105...1-110
-----------------------------------8<------------------------------------------

93c46 - 1K (64x16) CMOS Serial Electrically Erasable PROM.
Pin configuration:
      =====                      =====
 CS -|1 U 8|- Vcc           NU -|1===8|- Test
CLK -|2   7|- Test         Vcc -|2   7|- Vss
 DI -|3   6|- Test          CS -|3   6|- DO
 DO -|4   5|- Vss          CLK -|4   5|- DI
      =====                      =====
  DIP, SOIC 93C46               SOIC 93C46X

DC Characteristics:
                                 min     max             conditions
Vcc detector treshold, V         2.8     4.5
High level input voltage, V      2.0    Vcc+1
Low level input voltage, V      -0.3     0.8
High level output voltage, V     2.4                    Ioh= -400 uA
Low level output voltage, V              0.4            Iol= 3.2 mA
Input leakage current, uA                10             Vin= 0V to Vcc (1)
Output leakage current, uA               10             Vout= 0V to Vcc (1)
Internal capacitance, pF                  7             f= 1MHz
Operating current, mA                     4             f= 1MHz
Standby current, uA                      100            CS= 0V, Vcc= 5.5V
Note (1): Internal resistor pull-up at Pin 6.

AC Characteristics:
                                                         min   max   conditions
Clock frequency, MHz                           Fclk             1
Clock high time, ns                            Tckh      500
Clock low time, ns                             Tckl      500
Chip select setup time, ns                     Tcss       50
Chip select hold time, ns                      Tcsh       0
Chip select low time, ns                       Tcsl      100
Data input setup time, ns                      Tdis      100
Data input hold time, ns                       Tdih      100
Data output delay time, ns                     Tpd              400   Cl=100 pF
Data output disable time (from CS=low), ns     Tcz              100   Cl=100 pF
Data output disable time (from last clock), ns Tddz             400   Cl=100 pF
Status valid time, ns                          Tsv              100   Cl=100 pF
Program cycle time (Auto Erase & Write), ms    Twc         2
                                                          15        ERAL & WRAL
Erase cycle time, ms                           Tec         1

Synchronous data timing:

                 Tckh             Tckl
          |______________| |               | __________________
CLK______/|               \|_______________|/|                 \___________
          |                                  |
     |Tdis| Tdih  |                          |
____ | __________ | _________________   _____________   ___________________
 /\ \ /  valid   \ /\ /\ /\ /\ /\ /\ \ /   valid     \ /\ /\ /\ /\ /\ /\ /\
DI/_/ \__________/ \/_\/_\/_\/_\/_\/_/ \_____________/ \/_\/_\/_\/_\/_\/_\/
          |                                  |
      |Tcss                                  |                   | Tcsl|
      |__________________________________________________________|     |____
CS___/    |                                  |                   |\___/
          |                                  |                   |
          |  Tpd   |                         | Tpd |             |Tcz|
__________________ | _____________________________ | _______________ |
                  \ /          valid              \ /    valid      \|_HIGH_
DO________________/ \_____________________________/ \_______________/



Instruction set:

instruction start   opcode       address       number of     data out   CLK
             bit   OP1 OP2                      data in                cycles
  READ        1     1   0   A5 A4 A3 A2 A1 A0                 D15-D0     25
  WRITE       1     0   1   A5 A4 A3 A2 A1 A0   D15-D0      (RDY/^BSY)   25
  ERASE       1     1   1   A5 A4 A3 A2 A1 A0               (RDY/^BSY)    9
  EWEN        1     0   0    1  1  X  X  X  X                 High-Z      9
  EWDS        1     0   0    0  0  X  X  X  X                 High-Z      9
  ERAL        1     0   0    1  0  X  X  X  X               (RDY/^BSY)    9
  WRAL        1     0   0    0  1  X  X  X  X   D15-D0      (RDY/^BSY)   25

Read mode:

 DI     1  1  0  A5 A4 A3 A2 A1 A0
 DO                                D15 D14 D13 D12 D11 ... D2 D1 D0

Write mode:

 DI     1  0  1  A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 ... D2 D1 D0
 DO                                                                   BSY RDY

Erase mode:

 DI     1  1  1  A5 A4 A3 A2 A1 A0
 DO                                BSY RDY

Erase/Write enable/disable (EWEN,EWDS) mode:

 DI     1  0  0  1/0 1/0  X  X  X  X

Erase all (ERAL) mode:

 DI     1  0  0  1  0  X  X  X  X  X
 DO                                  BSY RDY

Write all (WRAL) mode:
                                     D15          D1 D0
 DI     1  0  0  0  1  X  X  X  X  X  X  X  X  ... X  X
 DO                                                     BSY RDY



 ⮬  p筨 ᠭ 24C01, 24C02, 24C04, 24C16, 59C11, 85C72,
85C82, 85C92, 93C06, 93C46, 93C56, 93C66, ER59256, 28C04, 28C16, 28C17, 28C64.

----------------------------------8<-----------------------------------------

 p, . ᥣ p襣.

Alexej

--- GoldED 2.40
 * Origin: * AV_Point - Riga, Latvia * (2:5100/22.1)

