 RU.HACKER (2:5020/299)  RU.HACKER 
 From : Alexander Yanovsky                  2:5020/443.24   Thu 28 Dec 95 19:16 
 Subj :  OPTI895 - ⠩!                                             


᪮   y. ⥫ pﭨ  稯  y.
NB:  H!!! p졠   p᫠ p ᠩ,  
   ᠭ.

-------- OP895GEN.DOC
OPTi895 General Purpose Registers
Hacked by PC޴awk

I/O Ports: 22h Index, 24h Data

[Reg 20h]
bit 7,6  <R/O> ? Revision {00}
bit 5    Cache Read Cycle X-2-2-2 if 1, X-1-1-1 if 0
bit 4    ? External Cache Buffer Output Control {1}
bit 3    Single ALE
bit 2    AT Cycle W/S (0 or 1)
bit 1    ? Keyboard Reset Control {1}
bit 0    ? Fast Reset {0}

[Reg 21h]
bit 7    Master Mode Byte Swap
bit 6    ? Keyboard Reset Delay (2us if 0) {0}
bit 5    ? Parity Check Disable {1}
bit 4    Ext. Cache ON / DRAM Burst OFF
bit 3,2  Cache Size (00=64K 01=128K 10=256K 11=512K)
bit 1    Cache Write 0 W/S (1 W/S if 0)
bit 0    Cache Read Cycle 2-X-X-X if 1, 3-X-X-X if 0

[Reg 22h]
bit 7    F000:64 R/O Shadow if 0, ROM to DRAM Copying if 1
bit 6    ? Shadow RAM at D000:64 {1}
bit 5    ? Shadow RAM at E000:64 {1}
bit 4    D000:64 R/O Mode
bit 3    E000:64 R/O Mode
bit 2    ? Hidden Refresh Disable {0}
bit 1    ? {0}
bit 0    Slow Refresh

[Reg 23h]
bit 7    EC00:16 Shadow
bit 6    E800:16 Shadow
bit 5    E400:16 Shadow
bit 4    E000:16 Shadow
bit 3    DC00:16 Shadow
bit 2    D800:16 Shadow
bit 1    D400:16 Shadow
bit 0    D000:16 Shadow

[Reg 24h]
? Something related to DRAM configuration {05h}

[Reg 25h]
bit 7    ? {0}
bit 6,5  DRAM Burst Mode (00=3222 01=4333* 10=4333 11=5444)
bit 4    DRAM Write W/S
bit 3    <R/O> ? Fast Decode {1}
bit 2    <R/O> ? {1}
bit 1,0  ATCLK (00=CLKI/6 01=CLKI/5 10=CLKI/4 11=CLKI/3)

[Reg 26h]
bit 7    ? {0}
bit 6    ? C000: 0=R/W AT Bus, 1=Read AT Bus, Write Shadow RAM {0}
bit 5    C000:64 R/O Mode
bit 4    ? ROM Located at C000 {1}
bit 3    CC00:16 Shadow
bit 2    C800:16 Shadow
bit 1    C400:16 Shadow
bit 0    C000:16 Shadow

[Reg 27h]
bit 7    ? Enable Low NCA# {0}
bit 6    Fast AT Cycle
bit 5    AT Cycle Between I/O Cycles (0=3, 1=0)
bit 4    F000:64 R/O Mode
bit 3    Turbo mode (Ctrl-Alt-[+])
bit 2    ? {0}
bit 1    ATCLK Mode (0=14.318/2, 1=Synchro)
bit 0    ? {0}

[Reg 28h,29h,2Ah,2Bh]
? Non-Cacheable Blocks {FC 00 00 0F}

[Reg 2Ch,2Dh]
? {2C/3C C0} Reg.2C is R/O, 2D is related to shadowable segments

[Reg 2Eh]
bit 7    ? {0}
bit 6    E000:64 Cacheable L1
bit 5    D000:64 Cacheable L1
bit 4    C000:64 Cacheable L1
bit 3    EC00:64 Cacheable L2
bit 2    E800:64 Cacheable L2
bit 1    E400:64 Cacheable L2
bit 0    E000:64 Cacheable L2

[Reg 2Fh]
bit 7    DC00:64 Cacheable L2
bit 6    D800:64 Cacheable L2
bit 5    D400:64 Cacheable L2
bit 4    D000:64 Cacheable L2
bit 3    CC00:64 Cacheable L2
bit 2    C800:64 Cacheable L2
bit 1    C400:64 Cacheable L2
bit 0    C000:64 Cacheable L2

-------- OP895PM.DOC
OPTi895 Power Management Registers
Hacked by PC޴awk

I/O Ports: 22h Index, 24h Data

[Reg E0h] {off:08/on:A8}
bit 7..4 ?
bit 3..0 <R/O> {1000}

[Reg E1h] {off:00}
bit 7..3 ? Set to 00100 on non-SMI, to 01100 on SMI
bit 2..0 System Timeout: 15"/2'/5'/15'/30'/45'/1h/4h

[Reg E2h]
bit 7..0 IRQ7..IRQ0 Monitor

[Reg E3h] {off:00}
bit 7..0 IRQ15..IRQ8 Monitor

[Reg E4h] {off:00}
bit 7..0 DRQ7..DRQ0 Monitor

[Reg E5h] {off:00}
bit 7    ? {0}
bit 6    Video RAM Monitor
bit 5    Video Ports Monitor
bit 4    HDD Ports Monitor
bit 3    FDD Ports Monitor
bit 2    Keyboard Ports Monitor
bit 1    Local Bus Device Monitor
bit 0    ? {0}

[Reg E6h,E7h] {00}

[Reg E8h,E9h] {08}

[Reg EAh] {off:00/on:F8}

[Reg EBh] {FF}

[Reg ECh] {00}

[Reg EDh]
bit 7    Screen Sleep (maybe bit 6?)
bit 6..0 ? {1010000}

[Reg EEh] {00}
bit 7    <R/O> {0}

[Reg EFh] {off:C0/on:40}

 ਬ  㢥७  ᮢ襭襬   ⥭.
                       Alexander Yanovsky, aka PC Hawk

--- GoldED 2.42.G0214+
 * Origin: [PC޴awk] (2:5020/443.24)

